Non-volatile memory devices, such as universal serial bus (USB) flash memory devices or removable storage cards have allowed for increased portability of data and software applications. Flash memory devices can enhance cost efficiency by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 3 bits per cell, 4 bits per cell, or more.
Storing multiple bits of information in a single flash memory cell typically includes mapping sequences of bits to states of the flash memory cell. For example, a first sequence of bits “110” may correspond to a first state of a flash memory cell and a second sequence of bits “010” may correspond to a second state of the flash memory cell. After determining that a sequence of bits is to be stored into a particular flash memory cell, the flash memory cell may be programmed to a state corresponding to the sequence of bits.
A particular mapping of sequences of bits to states used by a flash memory device impacts a relative reliability of bits stored at flash memory cells. To illustrate, if a flash memory cell is programmed to a first state (corresponding to an analog threshold voltage V and associated with the data “110”) but is incorrectly read as a second state (corresponding to an analog threshold voltage V+ΔV and associated with the data “010”), a bit error occurs at the most significant bit (i.e. “1” becomes “0”), but no error occurs at the middle bit or at the least-significant bit. In other words, there is a transition in the most significant bit (MSB) between the two states, but there is no transition in the other bits. Logical pages of data may be stored based on a common bit position in multiple flash memory cells. A read error between adjacent states (i.e. a state whose analog threshold is V is mistakenly read as a state whose analog threshold is V+ΔV) may have a probability p. A read error between non-adjacent states (e.g. states whose analog threshold voltage difference is typically greater than three times ΔV) may have a probability that is very small compared top and that may be approximated as zero. The number of data errors in a logical page may therefore be approximated to be proportional to the number of pairs of adjacent states whose corresponding bit in the logical page changes between the two states. Such a pair occurs whenever there is a transition of sign between a state and an adjacent state. Therefore, logical pages with many such pairs (i.e. with many transitions from 1 to 0 and from 0 to 1) will have more errors than pages whose number of transitions is smaller, provided that the states are uniformly spread within the voltage window. Some logical pages may be more reliable than other logical pages. Unequal reliability of logical pages may impact certain flash memory access methods and performance.